Circuit for detection of internal microprocessor watchdog device execution and method for resetting microprocessor system

ABSTRACT

In a circuit for detection of internal microprocessor watchdog device execution comprising a microprocessor ( 6 ) with the internal watchdog device and with an input/output line ( 11 ) transmitting information about microprocessor reset, and a device for resetting the microprocessor system, to the input/output line ( 11 ) transmitting information about microprocessor ( 6 ) reset, a clock input CK is connected, which triggers the flip-flop ( 12 ), whose data input D and an inverted reset input /R are connected to the output of the device ( 19 ) for resetting the microprocessor system, and the inverted flip-flop ( 12 ) output /Q is connected to the input of the device ( 19 ^) for resetting the microprocessor system.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a National Stage Application of International Patent ApplicationNo. PCT/PL03/00058, with an international filing date of Jun. 17, 2003,which is based on Polish Patent Application No. P-354827, filed Jul. 1,2002.

TECHNICAL FIELD

The invention relates to a circuit for detection of internalmicroprocessor watchdog device execution and a method for resetting amicroprocessor system.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit for detection of internalmicroprocessor watchdog device execution and a method for resetting amicroprocessor system.

2. Brief Description of the Background of the Invention Including PriorArt

A watchdog device is employed in microprocessor systems to constantlymonitor if the microprocessor properly executes its programs. A properlyfunctioning microprocessor periodically performs certain activities, forinstance storing a value in a register, sending an impulse to one of itsoutputs, or reading data. The watchdog device monitors these activitiesand if they do not occur in a specific period of time, it restarts themicroprocessor to restore the proper execution of microprocessorprogram.

In the existing systems, the watchdog device is built into the internalstructure of the microprocessor, or constitutes a separate externalcircuit. Taking into account its functionality, the watchdog device, onits activation, may restart the microprocessor or the whole system. Incase of a restart of the microprocessor itself, the restart of the wholesystem must be executed by the microprocessor. Some of themicroprocessors having an internal watchdog device are provided with anoutput pin that provides information about activation of the watchdogdevice. Such information may be used for a restart of the whole system.

In a typical system, the clock impulse generator sends signals to themicroprocessor, to the watchdog device and to other circuits of thesystem. In case where the watchdog device is in a form of a clockimpulse counter, it sends a microprocessor a start or a reset signalafter having counted a certain amount of impulses. Under normaloperating conditions, the microprocessor sends a signal to the watchdogdevice to avoid a reset. This signal causes the watchdog to restartimpulse counting. Therefore, during normal microprocessor operation thewatchdog device is periodically reset. When the microprocessor operationis disrupted, the signal resetting the watchdog device will not be sentearly enough and the microprocessor will be reset.

A common problem occurs while writing data to a Flash-type memory, inwhich the program executed by the processor is stored, when it isnecessary to control the access to this memory and set it to write orread mode. For a proper operation of the system, both the write and readoperations must be performed without disruptions. If any disruption inmicroprocessor operation occurs and the microprocessor is reset by thewatchdog device, it is necessary to reset the Flash-type memory as well.This requires a reset of the whole system.

One of the known solutions to avoid the problem of access to the Flashmemory is presented in the U.S. Pat. No. 5,983,330 entitled“Microcomputer with Watchdog Timer Setting Suppressing Interrupt RequestProcessing Over Memory Data Write Operation to Flash Memory”. Thatsolution suggests disconnecting the watchdog device from themicroprocessor while writing data to the Flash memory. However, this isnot an ideal solution. It requires controlling the output signal of thewatchdog device. Moreover, disconnecting the watchdog device increasesthe probability of system crash.

Another solution is presented in a European Patent Office patentapplication no. EP 0 945 770 A2 entitled _(“)Electronic control unit andmethod having program rewriting function”. It describes method forcontrolling a system while writing data to a Flash memory. The drawbackof this method is that the processor should signal its abnormaloperation.

SUMMARY OF THE INVENTION

1. Purposes of the Invention

It is an object of this invention to provide a circuit for detection ofwatchdog device execution more efficient than know circuits.

This and other objects and advantages of the present invention willbecome evident from the description which follows.

2. Brief Description of the Invention

In a circuit for detection of internal microprocessor watchdog deviceexecution comprising a microprocessor with the internal watchdog deviceand with an input/output line transmitting information aboutmicroprocessor reset, and a device for resetting the microprocessorsystem, to the input/output line transmitting information aboutmicroprocessor reset, a clock input CK is connected, which triggers theflip-flop, whose data input D and an inverted reset input /R areconnected to the output of the device for resetting the microprocessorsystem, and the inverted flip-flop output /Q is connected to the inputof the device for resetting the microprocessor system.

The input/output line transmitting information about microprocessorreset can be connected to the power supply voltage through an externalresistor.

The reset of the microprocessor system resulting from the reset of themicroprocessor can be performed when the inverted reset input /R and theflip-flop data input D are in a high state and the clock input CKchanges from a low to a high state.

The reset of the microprocessor system resulting from the reset of themicroprocessor can be blocked by a low state of the flip-flop invertedreset input /R.

In a method for resetting a microprocessor system comprising a circuitfor detection of internal microprocessor watchdog device execution,after disruption of microprocessor operation, an input/output line ofthe microprocessor is set to a high impedance state and a system resetsignal, generated by a flip-flop, is sent to a device for resetting themicroprocessor system, and after finishing the resetting of themicroprocessor system, the input/output line is set to a low state.

The microprocessor system can be reset, when the flip-flop has aninverted reset input /R, a data input D and a clock input CK, and theinverted reset input /R and the data input D are in a high state and theclock input CK changes from a low to a high state.

The reset of the microprocessor system resulting from the reset of themicroprocessor can be blocked by imposing a low state on the flip-flopinverted reset input /R.

The novel features which are considered as characteristic for theinvention are set forth in the appended claims. The invention itself,however, both as to its construction and its method of operation,together with additional objects and advantages thereof, will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The object of this invention is shown in implementation examples in theenclosed drawings, in which:

FIG. 1 illustrates a simplified schematic of a microprocessor, having aninternal watchdog device;

FIG. 2 illustrates a plot of signals generated by a watchdog device, aflip-flop, and a system reset circuit; and

FIG. 3 illustrates a fragment of a processor startup procedure,generating a signal used in detecting the activation of the watchdogdevice.

DESCRIPTION OF THE INVENTION AND PREFERRED EMBODIMENT

FIG. 1 presents a system comprising a processor 1, a Flash memory block16, a system reset circuit 19 and a flip-flop 12, responsible fordetecting a reset of the central processing unit (CPU) 6 activated bythe internal watchdog 2. The flip-flop 12 is triggered by a rising edgeof the clock signal CK, which results in outputting at the /Q output asignal that is input to its data input D. In addition, the flip-flopoutput can be reset asynchronously by a reset signal /R. The processor 1comprises a CPU 6, a watchdog device 2 and an external memory controller4. The CPU 6, in order to write data to the Flash memory 16, sends it tothe external memory controller 4 through the data bus 17. The externalmemory controller 4 sends the data to the Flash memory 16 through thebus 9. During the normal operation of the CPU 6, the CPU sends, inspecific time periods, a reset signal 5 to the watchdog 2. If thewatchdog 2 does not receive the reset signal 5 within a specific time,it sends a reset signal 3 only to the CPU 6. The reset of the CPU 6,initiated by the watchdog 2, without the reset of the whole system,including the reset of the Flash memory 16, may eventually cause asystem crash. For example, the CPU 6 may then read incorrect data fromthe Flash memory 16. If the program executed by the CPU 6 detects byitself an abnormal system operation, it can send a reset signal 8 to thesystem reset circuit 19, responsible for resetting the CPU 6, the Flashmemory 16 and other circuits. The system reset circuit has severalinputs, activating the reset signals 20. The reset circuit isresponsible for resetting specific attributes of various systemcomponents in a specific sequence. For example, the Flash memory shouldbe reset before resetting the processor, which enables the processor toread proper data from the memory. The system reset circuit 19 can beactivated also by other signals, for example by a reset signal 14 thatdetects power loss or by a manual reset signal 15.

The method for detecting the activation of the internal watchdog device2 and performing the reset of the whole system (not only of the CPU 6)is based on the fact that, after the reset of the CPU 6, the processorsets a high impedance state on its outputs 11, 18. Therefore, oneinput/output line 11 (WDOG_PIO) has been allocated for the purpose ofdetecting the activation of the internal watchdog device 2. In certainCPU 6 configurations, the input/output lines 11, 18 do not have internalresistors that connect the CPU 6 pins to the power supply voltageV_(cc). For such a configuration, presented in this description, anexternal resistor 10 has been added. It enables to obtain a high state(a logic “1”) on the WDOG_PIO input/output line 11 after the CPU 6 isreset and the input/output line 11 is set to a high impedance state. TheWDOG_PIO input/output line 11 of the CPU 6 is connected to the clockinput CK of the flip-flop 12. The system reset signal 20 is connected tothe data input D and to the inverted reset input /R of the flip-flop 12.By monitoring the input signals, the flip-flop 12 can detect when thesystem reset should be performed—by triggering the system reset circuit19 by a signal from the inverted /Q output through the line 13. Thetruth table for the flip-flop is presented below:

/R CK D /Q 0 X X 1 1 ↑ 1 0 1 ↑ 0 1

The truth table for the flip-flop 12 defines that the system reset isperformed when the inverted reset input /R and the data input D are inthe high state and the clock input CK changes from a low state to a highstate. A low state of the inverted reset input /R imposes a high stateof the inverted output /Q, despite the states of the clock input CK andthe data input D, which prevents the reset of the system.

FIG. 2 presents a plot of a System_reset signal 26 (triggered by thesystem reset circuit 19), a plot of the /Q signal 27 (triggered by theflip-flop 12), a plot of the WDOG_PIO signal 31 (triggered by the CPU 6)and a plot of the CPU_nreset signal 45 (triggered by the internalwatchdog 2). When the reset signal 21 is generated, the whole system,including the CPU 6, is reset. The reset of the CPU 6 results in settingthe input/output line 18 to a high impedance state. The WDOG_PIOinput/output line 11 of the CPU 6 is also set to the high impedancestate, and through the resistor 10 it is set to a high state 32. Afterthe reset procedure is finished 22, the CPU 6 executes a program thatresults in setting the WDOG_PIO input/output line 11 to a low state 33(a logic “0”) and performs further actions. The system starts its normaloperation. If the system operation is disrupted, the watchdog 2 sends areset signal 41 through the CPU_nreset output, which results in thereset of the CPU 6. Next, the CPU 6 sets the input/output lines 18 to ahigh impedance state. The WDOG_PIO input/output line 11 of the CPU 6 isalso set to a high impedance state, and through the resistor 10 it isset to a high state 34. In the meantime, the reset signal becomesinactive 42. The change in state 34 of the WDOG_PIO input/output line 11results in activation of the flip-flop 12. The output 13 of theflip-flop 12 is switched to a low state 28, thereby activating thesystem reset circuit 19, which results in activating at its output 20 areset signal of a low state 23. This signal switches the output 13 ofthe flip-flop 12 to a high state 29, which results in deactivationsystem reset signal. After the system reset is finished 24, the CPU 6,executing the processor startup program, sets the WDOG_PIO input/outputline 11 to a low state 35, enabling further system operation.

A proper operation of the described system requires setting the WDOG_PIOinput/output line 11 to a low state after each reset of the CPU 6, whichis for simplicity referred to as a processor in the further description.FIG. 3 presents a fragment of a procedure performed during the startupof the processor, responsible for setting the WDOG_PIO input/output line11 to a low state after the processor reset. The procedure starts fromthe processor reset 50. Initially, the processor sets all theinput/output lines to a high impedance state in step 51. Next, itperforms environment initialization procedures in step 52, wheredifferent operation parameters are set up. After the initialization isfinished, the program from the Flash memory is executed in step 53. Thisprogram in its first steps allocates a specific input/output line 11,called WDOG_PIO, and sets it to an output mode in step 54. Next, it setsit to a low state in step 55. Next, in step 56, the processor continuesexecuting further commands of the program from the Flash memory.

It will be understood that each of the elements described above, or twoor more together, may also find a useful application in other types ofmethods for allocation of data differing from the types described above.

While the invention has been illustrated and described as embodied inthe context of a method for allocation of data for images in operatingmemory, it is not intended to be limited to the details shown, sincevarious modifications may be made without departing in any way from thespirit of the present invention.

Without further analysis, the foregoing will so fully reveal the gist ofthe present invention that others can, by applying current knowledge,readily adapt it for various applications without omitting featuresthat, from the standpoint of prior art, fairly constitute essentialcharacteristics of the generic or specific aspects of this invention.

What is claimed as new and desired to be protected by Letters Patent isset forth in the appended claims.

1. A circuit for detection of internal microprocessor watchdog deviceexecution in a microprocessor system comprising a microprocessor havinga reset input, an internal watchdog device generating a reset signal andconnected to the reset input, and an input/output line WDOG_PIOtransmitting information about microprocessor reset independently fromthe reset signal; a device for resetting the microprocessor system andhaving an activation input, a system reset output connected to the resetinput of the microprocessor and configured to generate a system resetsignal at the system reset output responsively to an activation inputsignal received at the activation input; a flip-flop having a clockinput CK connected to the input/output line WDOG_PIO of themicroprocessor, a data input D and an inverted reset input /R connectedto the system reset output of the device for resetting themicroprocessor system, and an inverted flip-flop output /Q connected tothe activation input of the device (19) for resetting the microprocessorsystem.
 2. The circuit according to claim 1 further comprising anexternal resistor connecting the input/output line WDOG_PIO to a powersupply voltage.
 3. The circuit according to claim 1, wherein reset ofthe microprocessor system resulting from reset of the microprocessor isperformed when the inverted reset input /R and the flip-flop data inputD are in a high state and the clock input CK changes from a low to ahigh state.
 4. The circuit according to claim 1, wherein reset of themicroprocessor system resulting from reset of the microprocessor isblocked by a low state of the inverted reset input /R of the flip-flop.5. A circuit for detection of internal processor watchdog deviceexecution in a microprocessor system comprising a microprocessor havingan input/output; an internal watchdog device linked to themicroprocessor via reset signal lines and activating the microprocessor;a flip-flop having a data input D, an inverted reset input /R connectedwith the data input D, an inverted output /Q for resetting themicroprocessor, and a clock input CK connected to the input/output ofthe microprocessor via an input/output line transmitting informationabout microprocessor reset; a device for resetting the microprocessorand linked to the inverted output /Q and the inverted reset input /R ofthe flip-flop and the microprocessor; and an external resistorconnecting the input/output line transmitting information about themicroprocessor reset to a power supply voltage.
 6. A microprocessorsystem comprising: a microprocessor having a reset input, an internalwatchdog device generating a reset signal and connected to the resetinput of the microprocessor, and an input/output line WDOG_PIOconfigured to transmit information about microprocessor resetindependently from the reset signal; a system reset circuit having anactivation input, and a system reset output connected to the reset inputof the microprocessor and configured to generate a system reset signalat the system reset output responsively to an activation input signalreceived at the activation input; a flip-flop having a clock input CKconnected to the input/output line WDOG_PIO of the microprocessor, adata input D and an inverted reset input /R connected to the systemreset output of the system reset circuit, and an inverted output /Qconnected to the activation input of the system reset circuit.
 7. Themicroprocessor system according to claim 6, further comprising a Flashmemory having a reset input connected to the system reset output of thesystem reset circuit.